1. Field of the Invention
The present invention relates to the microelectronic technology, more specifically, relates to a method of forming the gate with a LELE double pattern.
2. Description of the Prior Art
In the technology node of 32 nm and below of the photoetching process, the resolution index requirement thereof exceeds the limit of the optical lithography platform. A series of measures were adopted to solve the problem. As the ITRS (International Technology Roadmap for Semiconductors) shows, the DPT (double patterning technology), the EUV (extreme ultraviolet) and the EBL (electron beam lithography) are highly expected.
DPT splits a set of high-integrated circuit patterns into two and more low-integrated circuit patterns. The mask is manufactured respectively, and is completed exposing and etching in order, and then is merged into the high-integrated circuit pattern desired.
With the development of technology of the software and hardware of the photoetching equipment, the resolution and technical life of 193 nm immersion optical lithography platform are extended accordingly. The photoetching technologies of the immersion photoetching machine, of the EUV and even the smaller technology node are developed.
According to the research, the process of LELE (Litho-Etch-Litho-Etch) is the most popular process of DPT. This process forms the desired pattern by twice lithography and etching. There are two types for the desired pattern: the line and the trench.
FIG. 1a is a diagram of the traditional DPT with the first photolithography process. FIG. 1b is a diagram of the traditional DPT with the second photolithography process. FIG. 1c is a diagram of the traditional DPT with the process of LELE. As shown in FIGS. 1a-1c, the resolution of 193 nm immersion machine, such as NXT-1950i, has the HP (half pitch) of 38 nm, in order to satisfy the active layer of nodes in 22/20 nm and the design for poly gate. As shown in FIG. 1a, the Exposure 1 is formed by the first photolithography process. And as shown in FIG. 1b, the Exposure 2 is formed by the second photolithography process. Then the final contour is formed by the Exposure 1 and Exposure 2 with the process of LELE.
In the traditional processing for poly gate in 22/20 nm node, the main method is lithography and etching the polysilicon just by once, and the ODL (organic under layer) with spin-on is used to fill the patterns under layer. The SHB (Si-based hardmask) is used as a hardmask for the second photolithography. Finally, the bottom anti-reflective layer and the photo resist are formed a structure before the second exposing, that means the silicon oxide is used as a hardmask in the process of etching the polycrystalline silicon.
As the ODL and SHB are new materials and their cost is high, it is not often used for the process of the nodes in 40 nm and above. If these new materials are used in the process of the nodes in 28 nm and below, that will cost a lot of time and money.
Chinese Patent (CN 101303525A) has disclosed a method of double patterning. The method uses a filling material which is soluble in the developing solution to fill the trench with repeated layers and baking. Then the remnant fillers are removed by the repeated processes of developing. In another words, the flatness of silicon wafer is improved by the processing of double patterning with the developed filler. It also reduced the adverse effects of the trench filling to the accuracy of lithographic and the focal depth of subsequent lithography.
Chinese Patent (CN 101446760A) disclosed a method of double patterning for lithography, and the process comprises the following steps: a first photoresist layer is formed on the substrate at first, and the first photoresist layer has at least one opening, then the first photoresist layer is solidified. A second photoresist layer is formed on the substrate, then the first photoresist layer and the second photoresist layer are removed to expose the substrate, and making a smaller interval between the first photoresist pattern and the second photoresist pattern.